module clk_div #(
    parameter N = 500
) (
    input      CLK,
    output reg CLK_out
);
  reg  [9:0] CNT;  // 定义 10 位计数器
  wire       COUT;  // 计数器的进位输出
  always @(posedge CLK) begin
    if (CNT == N - 1) begin
      CNT     <= 0;
      CLK_out <= ~CLK_out;
    end else begin
      CNT <= CNT + 1'b1;
    end
  end
endmodule